Testing Technique for Digital Circuits

In this paper, we present a method of testing digital circuits during normal operation. The resources used to perform on-line testing are those which are inserted to alleviate the off-line testing problem. The off-line testing resources are modified such that during system operation they can also observe the normal inputs and outputs of a combinational circuit under test. The normal inputs to the circuit under test are compared with test vectors in its test set. When a normal input matches a test vector, the circuit output for such an input is typically compressed into a developing signature. When all of the test vectors in the test set have appeared as normal inputs, the signature is read and verified. With this method, the length of time required for all of the test vectors to appear, possibly in some order, among the normal inputs to the circuit under test is of considerable importance. We refer to this as the test latency and give analytical methods for its computation with verification by simulation. We also describe a hardware structure for implementing the concurrent test method and identify a number of approaches for reducing test latency. Zndex Terms-Concurrent testing, test latency, built-in-self-test, VLSI testing, testable design.